ML-driven investigation of non-ideal effects in multi-gate MOSFET characteristics for sub-10 nm technologies

Abstract The continuous drive to ultra-scaled transistor technologies, e.g., 7 nm, 5 nm, and beyond, has placed non-ideal effects at the center of VLSI design challenges. Subthreshold leakage, gate leakage, parasitic capacitances, mobility degradation, and process-induced variability pose significant challenges to accurate power estimation and optimization in MOSFET. Standard power estimation methods often struggle to incorporate these factors making them somewhat limited in advanced technology nodes. This research addresses the increasing need for high-quality power estimation methods by creating a hybrid machine learning (ML) model that includes these non-idealities in the power estimation work-flow. With a hybrid DRC framework (Deep Neural Network, Random Forest, CatBoost), the model was trained on simulation data generated by TCAD and executed within Visual Studio. To evaluate performance, the proposed hybrid model was created based on four other models, RF, DNN, an Artificial Neural Network (ANN), and a hybrid XGBoost model. The result data showed that the proposed hybrid had a maximum prediction accuracy of 96.31%, which is a significant improvement over traditional methods. This level of performance demonstrates the capability of hybrid ML models to improve power estimation in the VLSI design flow, which can shorten development cycles and improve design dependability.