Reducing Mechanical Stress Sensitivity of Integrated Circuits Through Component Rotation in Layout

This paper presents a method for reducing mechanical stress sensitivity that focuses on layout optimization. Mechanical stress is caused by IC packaging and can potentially bring the circuits out of specifications, but stressaware device models are not standard in circuit simulators. This limits the ability to simulate the stress effects. The proposed methodology utilizes the developed stress-dependent MOSFET and resistor models for circuit simulations to find the optimal layout topology. It is shown that by rotating critical circuit parts in the layout, the sensitivity to stress can be reduced without changing other circuit characteristics. An example procedure is performed on a CMOS reference current source and the simulations show that the stressinduced change in output current can be reduced by 25 % in the worst case across all corners by rotating only a single reference resistor.