HW/SW Co-Design for a Variational AutoEncoder Targeting Anomaly Detection on FPGA

Variational AutoEncoder (VAE) is a generative model based on autoencoders, utilizing a latent space with a probabilistic distribution to generate new data. VAE is applied in various fields, such as image generation, data compression, and text generation. This paper proposes a VAE-based anomaly detection system implemented on an FPGA. The design applies co-design techniques, optimizing the model in software and accelerating the whole model in hardware using High-Level Synthesis. Our proposed model reduces the model size by a factor of 10, with a slight accuracy drop when compared to the reference model in [1]. The proposed model is then retrained with a 16-bit fixed-point representation instead of a 32-bit floating-point. The hardware implementation results on the Pynq-Z2 development board show that the proposed VAE accelerator runs 10 times faster than the software-only version running on a laptop computer while occupying a small area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2 5, 0 0 0}$</tex> slices on the programmable logic.