FPGA-Based Design and Implementation of Processing Element Array for Convolutional Neural Networks

Convolutional Neural Networks (CNNs) are essential in AI for image tasks like facial recognition and object detection. While they improve accuracy, deploying them on hardware is challenging due to high computational and memory demands, requiring efficient accelerators to balance speed, power, and resources. In this study, we designed and implemented a computational unit for CNNs, including components such as a convolutional accelerator, pooling, fully connected layers, and an activation function. This study utilizes weight stationary (WS) to minimize data movement and reuse partial sums based on spatial architecture with an array of processing elements (PEs). To the end, the proposed accelerator achieves an inference speed of 33.53 frames per second at 250 MHz, consumes power of 6.34 W and this accelerator achieves a throughput of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{5 4. 9 0}$</tex> GOPS. The model ontain an accuracy of 98% in software and 95% after hardware simulation with the customized AlexNet model on MNIST dataset.