High-Efficiency 4:2 Compressor Designs: A Comparative Study on Hardware Cost and Error Trade-Offs

Approximate computing enhances energy, area, and performance in error-resilient applications like image processing and ML. This paper proposes two novel <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4: 2$</tex> compressors optimized for hardware efficiency while preserving accuracy. Integrated into an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8 \times 8$</tex> approx. multiplier with a PPR structure, our compressors achieve significant gains in hardware and error metrics. We benchmark them against state-of-the-art designs, evaluating area, power, delay, PDP, and PDAP, along with error metrics (NMED, MRED, PRED). Experimental results show Compressor I reduces power by 8.2%, PDP by 11.7%, and PDAP by 9.5% over conventional designs. Trade-off analysis highlights compressors near the origin in error-efficiency plots as optimal in cost and accuracy. Our designs outperform existing architectures, making them ideal for power-efficient AI/ML accelerators and high-performance applications. FPGA validation (Vivado), ASIC synthesis (Genus, TSMC 65nm), and Python-based error analysis confirm accuracy and reliability.