A 12-Bit 100MS/s SAR ADC with Sub-Radix and Optimize Digital Delay Path

This paper introduces a 12-bit sub-radix successive approximation register (SAR) analog-to-digital converter (ADC) operating at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 0 0 ~ MS/s}$</tex>. The design employs an optimized digital control logic with a reduced delay path to enhance conversion speed; meanwhile, shortening the decision time in the SAR algorithm increases susceptibility to comparator instability or settling of capacitor digital-to-analog (CDAC). To mitigate this, a redundancy bit is implemented to correct erroneous decisions. The proposed architecture achieves a signal-to-noise-and-distortion ratio (SNDR) over 70 dB, corresponding to an effective number of bits (ENOB) of 11 at the Nyquist rate, and consumes 2.85 mW with a 1.2 V power supply.