High-PSR Capacitor-Less LDO with Enhanced Bandgap Reference in 65nm CMOS Technology

This paper presents a capacitor-less lowdropout regulator (LDO) designed and simulated in a 65 nm CMOS process, achieving high power supply rejection (PSR) across the low-to-mid frequency range while ensuring enhanced loop stability. The proposed LDO integrates a bandgap reference (BGR) with two key techniques to improve PSR performance. Stability is further enhanced through Miller compensation and feedforward compensation. Overall results indicate that the LDO achieves a PSR ranging from 70 dB to 96 dB at 1 kHz under process, voltage, and temperature (PVT) variations. The measured line regulation is 0.04 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{mV}/\mathrm{V}$</tex>, with a quiescent current of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$140 \mu \mathrm{A}$</tex>. The regulator supports a maximum load current of 300 mA while operating over a supply voltage range of 1.8 V to 2.5 V.