Implementation of Memory Built-In Self-Test

Modern integrated circuits rely more and more on embedded memories such as SRAM, DRAM, and ROM, which constitute a significant portion of SoC designs. Since these memories are designed for higher frequencies and dense data storage, they are prone to several possible faults. Traditional external ATE testing has its challenges owing to high cost and limited access to deeply embedded memories. To overcome these, this paper is proposing an efficient MBIST architecture that integrates the FSM-based controller and advanced fault simulation techniques. The solution concentrates on detecting and diagnosing the common memory faults such as stuck-at, transition, and coupling faults by implementing the MARCH <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{X}$</tex> algorithm on a 16-byte memory cell. The approach promises high fault coverage with minimal overhead in terms of resources, making memory operations both reliable and fault-tolerant in advanced semiconductor designs.