Concurrent ATE Testing of MSIP PHYs in SOC via Scan Streaming Fabric

Modern System-on-Chips (SOCs) are increasingly complex, integrating a diverse array of digital, analog, and mixed-signal IP blocks, including high-speed PHYs like PCIe, USB, UFS, and HBM. Ensuring the quality and reliability of these on Silicon requires numerous test methodologies, spanning Slow-ATPG, At-speed ATPG, MBIST, memory repair, and dedicated tests for analog components like PLLs, FLLs, and the various PHY interfaces. While test patterns for the core digital logic, such as ATPG and MBIST, often contribute a smaller portion to the overall test duration, the testing of complex analog blocks and high-speed mixed-signal PHYs typically constitutes a significant fraction of the total ATE test time. In this Paper we present 2 methods of Testing of the PHYs concurrently on ATE: Scheduling and Scan-Streaming Fabric and thereby saving the Test-time by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{5 0 - 7 0 \%}$</tex> for PHY Analog Tests. We also present a seamless flow of pattern porting from PHY IP level to SOC level via iJTAG 1687 IEEE protocol and a bridge module for efficient verification and man-hours optimization.