A Left Shifted Approach for Low Shift Power ATPG Decompression

Controlling power consumption during VLSI testing is critical for modern nanoscale technologies, particularly managing shift power within test compression frameworks. Conventional ATPG methods struggle to meet strict shift power budgets effectively when compression logic limits direct scan chain access. This paper introduces a novel power-aware ATPG technique centered on horizontal (scan-cells at same shift position) transition control, integrated seamlessly with decompressor logic. We propose a hardware-assisted mechanism mimicking adjacency fill to enable deterministic shift-hold capabilities via dedicated MUX logic controlled by ATPG. Furthermore, we detail a “Shift Left Strategy” employing ATPG guidance to proactively inform the test generator about established holdwindow constraints, preventing care-bit conflicts and significantly improving fault merging under tight power budgets. Experimental results on production designs demonstrate that, compared to a reference low-power technique, our approach achieves substantial reductions in test patterns (avg. 2.02x), test cycles (avg. 1.6x), and ATPG runtime (avg. 1.65x), alongside an average test coverage improvement of 0.79%, validating its effectiveness for stringent shift power targets (down to 25%).