Lite-CMOS Transition Fault Model (CTFM) for Legacy Design(s)

Advanced chips, built on innovative process nodes, are more susceptible to defects during manufacturing, making early detection critical. This necessity has driven the demand for extensive structural scan testing to screen for defects in the digital logic of System-on-Chips. The widely adopted Stuck-At (SA) and Transition-Delay (TD) scan ATPG fault models are not sufficient for screening out the defective parts and achieving low DPPM automotive parts. Targeted pattern generation for the SA and TD fault models is done only using port-level faults. Hence, the cell internal defects are not always visible via SA and TD patterns. The more recently developed Cell-Aware (CA) fault model has been successfully proven to be able to screen out the cell-internal defects. However, this approach incurs significant overhead, including CA-UDFM (user-defined fault model) generation. In this work, we present CTFM (CMOS Transition Fault Model), which uses custom UDFM files that target cell internal faults at the transistor level with less overhead compared with CA patterns. This is crucial for legacy designs, where fewer resources are typically allocated, especially compared to New Product Introduction (NPI) designs. A custom in-house diagnosis flow using our UDFM to improve scan diagnosis quality is also presented in this work.