Hybrid Bscan and Self-Test IOs to Reduce IO Test Time

As the SoC market becomes increasingly dynamic, cost optimization is crucial for success. Reducing test costs, especially for IOs, plays a significant role. While parametric and boundary scan methods are both used for IO testing, each has its drawbacks. This paper presents a novel Hybrid Bscan methodology for testing IOs, combining the fast and cost-effective boundary scan with the fault coverage of direct parametric testing via electrical probing. Silicon results on 7nm IO testing show a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5.4 x$</tex> reduction in test time for common IO specifications. As a further enhancement, we introduce ‘Bscan with self-test IOs’ method, which uses the comparator in high-speed IOs as an ADC, eliminating the need for electrical probing while maintaining fault coverage of parametric testing. Silicon measurement of 7nm IO on-die termination resistance using this approach yields a further <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{6 x}$</tex> reduction in test time.