Test Time Reduction in Current Sense Amplifiers via Optimized Current Range Across Wafer Touchdowns and Gain Reordering on V93K SMT8

In the present day, current sense amplifiers (CSA) are widely used in various applications such as power management, automotive, industrial, telecommunication etc where current monitoring is the crucial function. In this regard, testing CSA efficiently & accurately is a critical task for test engineers to ensure their performance meets the required standard. Traditional approach which keeps gain setting constant and varies current for different contracts has been noticed to consume higher test time. This paper presents an innovative approach for reducing overall test time in a wafer, by using adaptive current range across wafer touchdowns (TDs) and through gain-current reordering in a test program. The proposed approach has been verified on one of mixed signal devices on a wafer level using ADVANTEST V93K SMARTEST8(SMT8) ATE and found that test time has reduced by significant margin of about 37.8% compared to its traditional approach