Tester Time Savings for LBIST Diagnostics Using Enhanced Version of On-Chip MISR Signature Comparison with Self-Test and Bypass

With the shrinking time-to-market schedule, it is very important to be able to detect manufacturing defects and rectify the fabrication processes faster in order to have better quality products during mass production. Compression techniques have been adopted to shorten the scan chain lengths and in turn reduce the test time but, the data loss during signature generation makes the diagnosis harder and the difficulty increases with high data compaction techniques like Multiple-Input-Signature-Registers(MISRs) which are predominantly used in Logic Built-In-Self-Test(LBIST). These type of compactors are plagued by poor diagnostics, since it is very difficult to identify the locations of error-capturing flops per LBIST pattern basis which is the pre-requisite for locating the exact fault site. Though onchip MISR signature comparison methods with few extra gates have been proposed before to improve MISR diagnosability, the method of identifying faults in the added circuitry itself have not been analyzed. In this paper, we have introduced a self-test process to tackle this issue, along with a bypass mechanism to prevent yield loss if there are manufacturing defects in the extra logic. We have also introduced the on-chip compare method in addition to traditional LBIST in this paper and shown significant tester time savings during LBIST diagnostics.