Optimized Grouping for Packetized Scan Solutions

The increasing complexity and core count of modern System-on-Chips (SoCs) necessitates innovative testing methodologies. Traditional methods, constrained by limited pin count, struggle to significantly reduce test time and data volume. Packetized scan networks offer a promising solution by enabling efficient, high-speed, concurrent testing of multiple cores through packetized data streaming at higher delivery rate. However, effectively leveraging packetized scan solutions for optimal test efficiency requires careful consideration of core grouping strategies. Randomized grouping of cores can lead to inefficient testing and potential IOP overload and IR drop issues. The distribution of scan volume across cores is highly non-uniform, and combining cores with significant differences in scan volume leads to an increase in wasted bits. This paper proposes a novel, constraint-aware core grouping mechanism for concurrent testing that maximizes test efficiency while adhering to design constraints. Our methodology considers factors such as power clamp limits, thermal distribution, and test data overhead (wasted bits). By strategically clustering cores with compatible test requirements, we minimize test time and facilitate higher internal core frequencies during testing. This approach ensures efficient resource utilization while adhering to power and thermal constraints, ultimately enhancing the testability of complex SoCs. This methodology has been used to create core groupings for a real-world SoC, and the results have been validated on silicon.