Enhancing Memory Reliability: Integrating Error Correction Codes with Memory Built-In Self-Test for Effective Validation

Error correction codes (ECC) are techniques for detecting and correcting errors. The adoption of ECC is increasingly prevalent, driven by its ability to manage random defects in emerging memory technologies and to mitigate soft errors. When testing memories with ECC, the memory builtin self-test (BIST) logic must account for ECC's presence to accurately report the status during both manufacturing and insystem test. This paper details the innovations to memory BIST logic and the testing sequences to validate memories integrated with ECC, including those with redundancy.