Novel Post Silicon Validation Strategies for the New Era of UCIe Chiplets

The Universal Chiplet Interconnect Express (UCIe) standard marks a new era in SoC design by enabling the seamless integration of heterogeneous chiplets from multiple suppliers and process nodes into a single package. However, post-silicon validation of UCIe IP poses challenges due to the inpackage high-speed I/O links and lack of BKM's for this new technology. Our team validated Intel's first UCIe-compliant silicon, and in this paper, we outline the challenges and solutions across various post-silicon validation functions. Our learnings will help provide robust die-to-die link testing on the many upcoming products that have adopted our UCIe IP.