Novel Approach for Implementation and Validation of Scan Dump Debug Methodology

Scan Dump is useful debug technique used for debugging functional failures during field operation or in the lab. Typically, combination of in-house HW and SW based methodology is used to implement Scan Dump, but in-house methodology poses significant challenges for complete verification of scheme and scalability across different SoCs. This paper describes a novel and scalable approach to implement and verify Scan Dump operation. Approach involves inserting H/W components required for Scan Dump operation along with regular structural DFT components like Scan Streaming Network (SSN), Embedded Deterministic Test (EDT) and On Chip Clock Controllers (OCC) at physical PNR block level. Custom H/W connections are made to merge Scan Dump operation path into structural test IJTAG network. Scheme allows to verify Scan Dump operation completely at partition level without depending on SoC level infrastructure. All required validation collaterals can be generated at partition level and retargeted at SoC level.