Effective 3D IC Interconnect Test Using Defect Distance and Bump Placement Location

The power, performance and area (PPA) advantages offered by a multi-die package depend on the short, fast and low power die-to-die (D2D) interconnects that connect different chiplets in the system. Physical bumps comprising the interconnects are arranged in either rectangular or hexagonal grid patterns on the chiplet interface. These interconnects need to be properly tested for open and short defects to ensure proper connectivity between any two chiplets. Depending on the process node and the yield ramp stage, the size of the area of contamination may vary, leading to short defects beyond the immediate bump neighbors. In this paper we present an industrial flow where short defect candidate pairs are computed using (a) user-defined criteria for the area of defect for the bumps, and (b) layout information for the nets inside the interposer. Bump location information is automatically processed from a bmap file by the EDA tool and the user-defined fault model (UDFM) file is generated for ATPG to generate the patterns.