Test Selection and Scheduling for 3D-Stacked Chiplet-Based Designs

Integrating heterogeneous blocks like processors, analog/mixed-signal circuits, and memories into a single 2D chip is complex, resource-intensive, and prone to low yields due to large die sizes. Testing such large System-on-Chip (SoC) designs is also difficult. To address these challenges, the industry now uses chiplet-based 3D integration-dividing the SoC into smaller, independently manufactured units that are later assembled. This approach improves yield and design manageability. This paper focuses on testing 3D chiplets, addressing two key optimization problems: selecting the appropriate test method for each chiplet and scheduling the tests to minimize total test time while limiting peak power. We propose a greedy heuristic based on estimated test time and power.