Enhanced RTL Test Point Insertion Flow with Improved Functional Block Testability

This paper introduces a novel methodology to extend Register Transfer Level (RTL) test point insertion (TPI) capabilities to functional blocks (FB) encompassing operators such as comparators, arithmetic and logical reduction operators, and shifters. The proposed methodology leverages a function-call-based technique for precise back-annotation of functional block expressions and the insertion of test point logic at targeted nodes. By effectively isolating complex regions within RTL designs and enabling the placement of control points and observe points, this approach achieves higher granularity in improving test coverage while preserving design optimization during synthesis. Additionally, it addresses challenges related to expression and logic sharing, ensuring correctness when RTL contexts overlap or diverge, with minimal impact on design area and performance, post-testpoint insertion. Furthermore, the methodology provides actionable feedback to RTL designers to identify locations unsuitable for test point insertion, thereby refining testability at RTL. Experimental results demonstrate the advantages of enhanced TPI to functional blocks which include reduced pattern count and minimal area overhead in comparison to gate level (GL) TPI.

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Publication Details

Published
2025-07-20
DOI
https://doi.org/10.1109/itcindia66078.2025.11141631
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
0.00
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article

Enhanced RTL Test Point Insertion Flow with Improved Functional Block Testability

Nilanjan Mukherjee, Naushad Ali, Nikita Naresh, Wilson Pradeep et al.
VLSI and Analog Circuit Testing
article

Enhanced RTL Test Point Insertion Flow with Improved Functional Block Testability

Nilanjan Mukherjee, Naushad Ali, Nikita Naresh, Wilson Pradeep, Oussama Laouamri, Karthick Prabhu B, Surya Phanindra Chatla
article en

Abstract

This paper introduces a novel methodology to extend Register Transfer Level (RTL) test point insertion (TPI) capabilities to functional blocks (FB) encompassing operators such as comparators, arithmetic and logical reduction operators, and shifters. The proposed methodology leverages a function-call-based technique for precise back-annotation of functional block expressions and the insertion of test point logic at targeted nodes. By effectively isolating complex regions within RTL designs and enabling the placement of control points and observe points, this approach achieves higher granularity in improving test coverage while preserving design optimization during synthesis. Additionally, it addresses challenges related to expression and logic sharing, ensuring correctness when RTL contexts overlap or diverge, with minimal impact on design area and performance, post-testpoint insertion. Furthermore, the methodology provides actionable feedback to RTL designers to identify locations unsuitable for test point insertion, thereby refining testability at RTL. Experimental results demonstrate the advantages of enhanced TPI to functional blocks which include reduced pattern count and minimal area overhead in comparison to gate level (GL) TPI.

Google (United States) (US), Siemens Healthcare (United States) (US)
Openalex Percentile: Top 75%
VLSI and Analog Circuit Testing
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