Modelling and Simulation of Heterojunction TFETs: Tackling Performance Challenges Through Machine Learning and Advanced Computational Techniques
Within the area of semiconductors, one of the most important objectives is to improve the TFET (tunnel field-effect transistor) performance. In this work, we analyse a heterojunction TFET architecture using ideal material combinations in the drain, channel, and source regions. This design aims to go beyond major constraints such ON current, subthreshold slope, and trans conductance. Investigating thoroughly helps one to find if the components from the III-V and IV categories influence the performance of the instrument. The results of the investigation show that while silicon (Si) is a good material for the source area, gallium arsenic ide phosphide (GaAsP) is the most appropriate material for the drain-channel (D/C) junction. These findings help us to better grasp the interactions of materials under many operating environments. Furthermore, by using artificial intelligence and machine learning techniques, our work helps to optimise TFET performance estimations and material choice. Using AI-driven modelling makes it much easier to handle chores like data analysis, material combination optimisation, and gadget efficiency enhancement for uses requiring extremely low power consumption. This work uses ordinary silicon materials, III-V, two-dimensional, and artificial intelligence-enhanced modelling techniques to demonstrate TFET technology development potential. This technique not only accelerates the design process but also helps to overcome traditional constraints, therefore opening the path for semiconductor devices with high performance and energy economy of usage.
Authors
- Ebtasam Ahmad Siddiqui (ORCID: https://orcid.org/0000-0002-0323-5441)
- Bandi Venkata Chandan (ORCID: https://orcid.org/0000-0002-9355-7291)
- Kaushal Nigam (ORCID: https://orcid.org/0000-0001-7588-0856)
- Adil Tanveer (ORCID: https://orcid.org/0009-0006-6971-8098)
Institutions
- National Institute of Technology Raipur (IN)
- Poornima University (IN)
Publication Details
- Published
- 2024-12-23
- DOI
- https://doi.org/10.1145/3745812.3745860
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00