Physics, modeling, and benchmarking of ULTRARAM: A compound semiconductor-based memory device

ULTRARAM is a promising emerging memory exhibiting high endurance, long retention, and ultra-low switching energy per unit area. This compound semiconductor-based non-volatile memory utilizes triple barrier resonant tunneling (TBRT) through InAs/AlSb heterostructures. In this work, we have proposed a physics-based compact model of ULTRARAM memory device that captures the real-time trapping/de-trapping of charges in the floating gate and used to calculate the device characteristics. In addition, we have performed numerical simulations of the TBRT stack using the Schrödinger equation inside the quantum well with mono-layer (∼0.6 nm) variations to check the impact on memory characteristics of the device. Array-level simulations and benchmarking highlight the promise of this technology.

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Publication Details

Journal
Journal of Applied Physics
Published
2025-09-02
DOI
https://doi.org/10.1063/5.0269780
Citations
2
Primary Topic
Semiconductor materials and devices
Type
article
Field-Weighted Citation Impact
1.46

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article

Physics, modeling, and benchmarking of ULTRARAM: A compound semiconductor-based memory device

Richard Beanland, Avirup Dasgupta, Peter Hodgson, Peter J. Carrington et al.
2 citations
Journal of Applied Physics
Semiconductor materials and devices
1.46
article

Physics, modeling, and benchmarking of ULTRARAM: A compound semiconductor-based memory device

Richard Beanland, Avirup Dasgupta, Peter Hodgson, Peter J. Carrington, Dominic Lane, M. Hayne, Shruti Mehrotra, Evangelia Delli, Abhishek Kumar, Musaibh Farooq Dar
article en
2 citations

Abstract

ULTRARAM is a promising emerging memory exhibiting high endurance, long retention, and ultra-low switching energy per unit area. This compound semiconductor-based non-volatile memory utilizes triple barrier resonant tunneling (TBRT) through InAs/AlSb heterostructures. In this work, we have proposed a physics-based compact model of ULTRARAM memory device that captures the real-time trapping/de-trapping of charges in the floating gate and used to calculate the device characteristics. In addition, we have performed numerical simulations of the TBRT stack using the Schrödinger equation inside the quantum well with mono-layer (∼0.6 nm) variations to check the impact on memory characteristics of the device. Array-level simulations and benchmarking highlight the promise of this technology.

Journal of Applied PhysicsVol. 138(9)
Indian Institute of Technology Roorkee (IN), GlobalFoundries (United States) (US), University of Warwick (GB), Lancaster University (GB)
Indian Institute of Technology Roorkee, Ministry of Education, India, Horizon 2020 Framework Programme, Engineering and Physical Sciences Research Council, Innovate UK
Openalex Percentile: Top 15%
Semiconductor materials and devices
1.46
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