Corrigendum: Density and energy level of near-interface trap estimated by analysis of threshold voltage shift due to positive bias stress in GaN planar MOSFETs with SiO₂ gate dielectric [Appl. Phys. Express, 18, 031002 (2025)]
Corrigendum: Density and energy level of near-interface trap estimated by analysis of threshold voltage shift due to positive bias stress in GaN planar MOSFETs with SiO₂ gate dielectric [Appl. Phys. Express, 18, 031002 (2025)], Ichikawa, Yuki, Ueno, Katsunori, Kondo, Tsurugi, Tanaka, Ryo, Takashima, Shinya, Suda, Jun
Authors
- Shinya Takashima (ORCID: https://orcid.org/0000-0002-3212-4521)
- Katsunori UENO
- Jun Suda (ORCID: https://orcid.org/0000-0002-5453-4943)
- Ryo Tanaka (ORCID: https://orcid.org/0000-0002-4058-7649)
- Tsurugi Kondo
- Yuki Ichikawa (ORCID: https://orcid.org/0009-0006-8881-0033)
Institutions
- Fuji Electric (Japan) (JP)
- Nagoya University (JP)
Publication Details
- Journal
- Applied Physics Express
- Published
- 2025-09-01
- DOI
- https://doi.org/10.35848/1882-0786/adf8af
- Primary Topic
- GaN-based semiconductor devices and materials
- Type
- article
- Field-Weighted Citation Impact
- 0.00