Full Custom Design and Implementation of 12-Bit Complex Multiplier

The complex multiplier is an important module used in co-processors, especially designed for signal processing in Graphical Processing Units (GPUs), Digital Signal Processors (DSPs), and certain Artificial Intelligence (AI) accelerators. These applications require a low area and low power. This work presents a novel strategy for complex number multiplication. The design is full custom and utilizes a circuit optimization technique. The complex multiplier is designed using the Bottom-up approach. It uses a radix-4 modified Booth encoder. These concepts are used for performance improvement. The process of multiplication is sped up as the radix-4 modified Booth encoder can decrease the rows of partial products to n/2, and carry-save adders are designed to add the partial products by using a smaller number of transistors to improve the speed of the addition process. Finally, an increase in speed, low power, and low area is achieved by the utilization of a smaller number of transistors overall. Hence, less silicon area is utilized. The design is implemented using Cadence tools for 12x12-bit signed and unsigned numbers and is simulated using ADE with Spectre simulator for both pre-layout and post-layout complex multiplier using 0.18μm technology. Novelty stems from its integrated approach of a new full-custom design strategy, meticulous circuit-level optimization, and the effective application of radix-4 Booth encoding to achieve a highly efficient 12-bit complex multiplier in terms of power, area, and speed.