A small-area and low-power readout circuit for a LOFIC CMOS image sensor

Lateral overflow integration capacitor (LOFIC) CMOS image sensors (CISs) can realize high-dynamic-range (HDR) imaging by combining high-conversion-gain (HCG) signal with low-conversion-gain (LCG) signal. However, LOFIC CISs require an analog-to-digital converter (ADC) and SRAM for both HCG and LCG signals, leading to higher power consumption and a larger circuit area compared to standard-dynamic-range (SDR) CISs. To address this issue, we propose a single-channel readout circuit for the LOFIC pixel with selector for HCG and LCG signals. When the HCG signal is selected, the A/D conversion of the LCG signal is halted, reducing the power consumption by 11.3 % on average. Furthermore, SRAM stores only the selected signal, reducing the readout circuit area by 7.9 %. A test chip of the readout circuit was fabricated with a 0.18 µm CMOS process. The dark noise of the HCG signal and the maximum charge of the LCG signal were respectively estimated to be 4.0 e-rms and 130 ke-, corresponding to a dynamic range of 90.2 dB.