Spacer Engineering for Performance Enhancement of FinFET Device Electrothermal Characteristics

This work develops a novel coupled electrothermal model for 14 nm fin-field-effect transistors (FinFETs) by integrating an enhanced drift-diffusion charge transport model with a thermal hydrodynamic model. The primary objective is to comprehensively analyze the device’s electrical and thermal characteristics, with a specific focus on the impact of different spacer dielectric materials. Key findings demonstrate that spacer choice critically influences performance: low-κ spacers significantly mitigate short-channel effects (SCEs), reducing drain-induced barrier lowering (DIBL) by up to 30% and enhancing transconductance (g<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>m</roman></sub>) by 15%–25%. Furthermore, symmetric low-thermal-conductivity (low-κ) spacers effectively reduce peak operating temperatures by 20%–35% by optimizing nanoscale heat conduction. Crucially, the model reveals a strong electrothermal feedback loop, where device self-heating directly exacerbates DIBL degradation. The novelty of this work lies in three key aspects: 1) it introduces the first unified modeling framework coupling charge transport and thermal kinetics specifically for FinFET electrothermal analysis, capturing interdependencies missed in prior approaches; 2) it establishes a direct, quantitative causal link between spacer dielectric properties (permittivity, thermal conductivity) and critical device metrics (DIBL, <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</roman><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>m</i></sub><italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"/>, temperature), providing new design guidelines for SCE suppression and thermal management; and 3) it uniquely validates the model against <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">both</i> experimental <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i>–<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics and transient temperature response data, confirming its accuracy for the 14 nm node. Results confirm that the proposed model accurately predicts the electrothermal behavior of 14 nm FinFETs and underscores spacer engineering as a vital strategy for optimizing device performance and reliability.