SiGe Channel Trench-Free Complementary FET With Direct Backside Contact for Suppressed Process Variation and High-Speed Applications

In this article, a novel SiGe channel trench-free complementary field-effect transistor (TF-CFET) with direct backside contact (DBC) is proposed for the first time. Compared to conventional complementary FET (CFET) with trench height (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>Tr</roman></sub><roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">)</roman> of 30 nm, TF-CFET demonstrates 21.0% reduction in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>GG</roman></sub> with the same dc performance. This can be attributed to the removal of the trench under the SiGe channels of bottom pMOS, which significantly reduces the area of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>GS</roman></sub>. Moreover, due to the absence of etching stop layer during the source/drain (S/D) recess, the over-etching thickness (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SD</roman></sub><roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">)</roman> has significant impact on dc and ac performance of traditional CFET. However, TF-CFET demonstrates perfect immunity to <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SD</roman></sub> variations. Additionally, the inverter, ring oscillator (RO), and static random access memory (SRAM) are investigated to further evaluate the ac performance of TF-CFET. The results show that, compared to the CFET with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>Tr</roman></sub> of 30 nm at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>DD</roman></sub>= 0.7 V, TF-CFET achieves 5.0% (7.1%) reduction in inverter rise (fall) time, 14.7% improvement in RO frequency, and 8.6% (11.1%) decrease in SRAM read (write) delay. Therefore, TF-CFET not only demonstrates enhanced capability in suppressing process variations but also is suitable for high-speed applications.