Bitline-Paired 2T SOT-MRAM Cell for Energy-Efficient Memory Operation

Spin-orbit torque magnetic random access memory (SOT-MRAM) has recently gained great attention due to its various benefits on memory implementation. However, SOT-MRAM suffers from high read and write energy consumption, making it difficult to replace conventional CMOS-based memories. This article presents a novel bitline (BL)-paired 2T SOT-MRAM cell structure, where the read and write path can be decoupled without causing bit-cell area overhead. Thanks to the separation of the read and write path, the BL parasitic capacitance can be reduced, which ultimately reduces read energy consumption. In addition, the read scheme tailored to the bit-cell structure is proposed to further enhance the read energy. The proposed cell also shows considerable write energy improvement when applying the write termination techniques that require simultaneous read and write operations. The HSPICE circuit simulations using the 28-nm CMOS technology show that the proposed BL-paired 2T SOT-MRAM cell with BL sharing achieves an average of 42.9% read energy savings, and an average of 56.8% write energy reduction compared to the conventional 2T cell in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$512\times 512$</tex-math> </inline-formula> array. The system simulations using the gem5 simulator also show that, compared to the conventional 2T cell, an average of 47.1% of dynamic energy can be saved in various SPEC2006 benchmarks when the BL-paired 2T cell is employed in L2 cache.