Redundancy-Interpolated Three-Segment DAC with On-Chip Digital Calibration for Improved Static Linearity

This paper presents a three-segment interpolating Digital-to-Analog Converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment uses a split-unit resistor structure (rA,rB) to improve post-calibration differential nonlinearity (DNL) by minimizing voltage step errors. A fully digital calibration algorithm is implemented to compensate for process variations, component mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180 nm CMOS process and is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The structure achieves post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) values of less than ±1 LSB. Simulation results validate the proposed design, demonstrating enhanced linearity and reduced area overhead compared with conventional segmented architectures.