Impact of Grain Boundaries on Zero-Temperature Coefficient Characteristics in a 3D-Stacked Transistor

In this paper, we investigate the zero-temperature coefficient (ZTC) characteristics of polycrystalline silicon (poly-Si) single-gate transistors with a silicon-on-insulator (SOI)-like structure, which offers thermal stability over a wide temperature range. While ZTC characteristics have been primarily utilized in analog and memory circuits, systematic analyses for logic transistors remain limited. The ZTC characteristic is quantitatively evaluated by considering various process parameters, including high-density three-dimensional (3D)-stacked structures. The effects of grain boundary (GB) location within the poly-Si, body thickness, and doping concentration on both the ZTC point and its temperature sensitivity are systematically analyzed. A new metric, ΔZTC, is defined to quantify the sensitivity of the ZTC point to the presence or absence of GBs. This metric is applied throughout the analysis. As a result, ZTC characteristics can be effectively optimized through structural parameter adjustment, and these characteristics are maintained or even enhanced when extended to multi-layer architectures. Notably, when GBs are confined to specific layers, the ΔZTC value is reduced by approximately 64.1% at a body thickness of 25 nm and by 62.5% at 7 nm, compared to the single-layer structure, indicating that temperature sensitivity can be significantly suppressed.