Analysis of n & p-channel heterojunction nanosheet MOSFET for logic circuit

Low power consumption and high speed are always concerns of IC designers. Increased transistor density increases the power density per unit chip and is a major parameter of chip reliability. Nanosheet transistors are a hybrid of multichannel, similar to MOSFET, and vertically aligned like FinFET, which is a suitable choice due to its reduced self-heating effects and high current drive capabilities. In this work, the heterojunction nanosheets demonstrate high switching current and good channel control due to multichannel and multigate features. The heterojunction nanosheet MOSFET is analyzed for electric field, channel potential, drain current, leakage current, threshold voltage, transconductance, subthreshold performance, and device switching current ratio. The analysis also explores the possibility of CMOS logic with the designed n & p-channel heterojunction nanosheet MOSFET at a 5 nm technology node. All the designs and simulations are performed using TCAD software, 2D and 3D visuals, and simulation data generation. The results show a very low leakage current and a good value of the Ion/Ioff current ratio. The designed n- and p-channel devices are also compared for compatibility in a CMOS logic circuit by implementing inverters, universal gate layouts, and verifying the functionality of the logic circuit.