Architectural Exploration and Implementation of CERN LHC Trigger Algorithm With FPGA

The upcoming high-luminosity upgrade of the Large Hadron Collider (LHC) at CERN will increase data rates to values far exceeding the capabilities of software-based processing systems. As a result, new methods are required to efficiently extract scientifically valuable information from the massive data streams produced by the LHC’s particle detectors. This article discusses the design of the tau lepton trigger algorithm using the field-programmable gate array (FPGA) technology. Given its complexity and demanding technical requirements, realizing the algorithm in FPGA is a challenging task. This article details the algorithm development using high-level synthesis (HLS), a technique to generate hardware descriptions from the C++ code. We discuss architectural solutions and optimizations explored during the design process, including algorithm partitioning and pipelining, optimization of pipeline stages, floorplanning, and probing of implementation strategies. The performed design space exploration helped to improve latency, solve area-related issues, and reduce routing congestion, enabling implementation of tau lepton trigger on FPGA.