Assessing the impact of process and design variations on reliability of complementary FET

• Investigate the reliability of complementary Field-Effect Transistors (CFETs). • Analyze the impact of individual process variations—including random dopant distribution (RDD), line edge roughness (LER), and metal gate granularity (MGG)—on CFET performance. • Examine the combined effect of all process variations on device behavior. • The influence of fin width on threshold voltage considering variability induced by LER. • The impact of grain size on threshold voltage variation, considering MGG. This paper comprehensively analyzes the reliability concerns of the Complementary FET (CFET), engrossing the design parameters and the variability effects. The impact of process-induced variabilities, such as random dopant distribution (RDD), line edge roughness (LER), and metal gate granularity (MGG), is extensively studied through well-calibrated TCAD models. Variation aware compact model based statistical analysis is used to analyze 100 random device samples, which shows a significant spread in the I DS -V GS curve (transfer characteristics). Electrical performance based on the grain size and fin width is also analyzed on both n and p-type device. Therefore, the variation in threshold voltage (V th ) is used to predict the early aging of the devices.