A Compact Low-Jitter All-Digital Fractional Output Divider Using Split-DTC-Based Background Calibration

This article presents a fractional output divider (FOD) incorporating a split-digital-to-time converter (DTC) architecture with fully digital background calibration for both gain errors and integral nonlinearity (INL) in DTC. The calibration scheme employs a mutual-reference mechanism between dual DTCs, where specifically configured DTC digital control words combined with redundancy and uncorrelated operations enable the bang–bang phase detector (BBPD) to extract both gain errors and INL from dual DTC phase differences. This allows the sign least-mean-square (sign-LMS) algorithm to iteratively update the gain calibration factor and INL error codes in the background. Fabricated in 28-nm CMOS technology, the prototype achieves a compact core area of 0.024 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using standard digital cells (except varactors in the DTCs), operating at 0.9-V supply voltage with 3.36-mW power consumption. Measurement results demonstrate a root mean square (rms) jitter of 191 fs and spurious power of −81 dBc in measurements performed at 123.46 MHz with a division ratio of 20.25.