Timestep-Parallel 4D Neuromorphic Computing Array Enabling High Computing Power Density and High Energy Efficiency

The timestep-based inference process of spiking neural networks (SNNs) presents two challenges for neuromorphic chip design: 1) additional storage overhead for membrane potentials, and 2) significant power consumption resulting from repeated access to computational data. To address this challenge, this work proposes a timestep-parallel 4D neuromorphic computing array of size <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N_T</i> × <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N_Z</i> × <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N_X</i> × <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N_Y</i>, simultaneously enabling parallel computing in temporal and spatial dimensions. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N_T</i> dimension supports timestep-parallel computing, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N_Z</i> dimension supports neuron-parallel computing, and the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N_X</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N_Y</i> dimensions are used for synapse-parallel computing. The architecture facilitates flexible data reuse across different dimensions (with weights reuse along different timesteps and spikes reuse along different neurons), significantly reducing storage access. Meanwhile, it treats the membrane potential as a short-term computational variable that can be stored in a small buffer, thereby eliminating large-scale membrane potential storage overhead and access. The reduction in data access and storage costs is beneficial for lowering system power consumption and enhancing synaptic energy efficiency. Ultimately, the architecture is evaluated using a 28 nm process library and demonstrates a high computing power density of 1160 GSOP/s/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a high synaptic energy efficiency of 0.36 pJ/SOP, surpassing related state-of-the-art works. This work significantly reduces the hardware cost of neuromorphic computing and is expected to enhance the competitiveness of neuromorphic hardware in contemporary artificial intelligence applications.