FPGA-Based Acceleration of Deep Learning Networks: Techniques and Applications

Deep learning models have made significant progress in fields such as image recognition and natural language processing. However, the increasing complexity and size of these models pose challenges for deployment on resource - constrained devices. This paper reviews the development of FPGA acceleration for deep learning models, with a focus on Convolutional Neural Networks (CNNs) and Transformers. The discussion of FPGA acceleration for deep neural networks is divided into software optimization and hardware optimization. On the software side, it includes network pruning, parameter quantization, and network architecture design. The paper also highlights the latest research on FPGA - based hardware accelerators for these models. Furthermore, it discusses future trends in the development of advanced hardware architectures and the deepening of software - hardware co - optimization to further improve the performance and energy efficiency of deep learning models.