On the role of power dissipation in the Post-BD behavior of FDSOI NanoWire FETs

Dielectric Breakdown, which has been associated with the progressive wear-out of the gate dielectric, has been one of the most detrimental failure mechanisms in CMOS devices. With downscaling, new device architectures and/or materials have been introduced, so, it is necessary to evaluate the BD impact at device (and circuit) level in these new structures. In this work, the dielectric BD and the post-BD behavior in largely scaled FDSOI nanowire transistors with high-k gate dielectric have been characterized, using the energy and the power dissipated by the device under test as key parameters. The experimental results evidence the presence of new detrimental effects for the device’s integrity beyond the traditional dielectric BD.