Physical Design and Analysis of RISC-V Processor Modules Using Synopsys EDA Tools (32nm)

The growing demand for high-performance and energy-efficient computing systems has accelerated the adoption of the RISC-V instruction set architecture (ISA). Its open-source nature, modular design, and flexibility have positioned RISC-V as a strong candidate for next-generation processors in embedded systems, AI accelerators, and edge devices. While numerous studies have addressed front-end design and FPGA implementations of RISC-V cores, relatively fewer works present detailed back-end (physical design) flows using industry-standard tools. This paper contributes a comprehensive RTL-to-GDSII implementation methodology of two representative RISC-V processor modules, an Integer Execution Unit (EXU) and a 5-stage Pipeline Core (RV32I baseline), using Synopsys EDA tools. The work emphasizes the complete back-end flow including logic synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff verification. A 32nm standard-cell technology library was employed to evaluate these modules. The flow achieved signoff-clean layouts with zero DRC and LVS violations, while successfully meeting timing closure targets for both modules at 500 MHz (EXU achieved 517 MHz, Pipeline Core achieved 505 MHz). The EXU occupied 81,110 µm² with 5.08 mW total power, and the Pipeline Core occupied 245,150 µm² with 13.62 mW total power. These results confirm that professional EDA flows can produce efficient, manufacturable layouts for open-source RISC-V designs, reinforcing the feasibility of integrating such architectures in commercial SoCs and serving as a practical reference for the VLSI community.