Comparison of CdTe Devices with Various Alloying Profiles

With CdTe PV technology growing quickly, it has become imperative to further increase the efficiencies of the technology. Graded CdSe<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf>Te<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</inf> (CST)/CdTe absorbers layers have been shown to be a high performing absorber structure. This work aims to investigate different processing schemes to produce high performance CdSe<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf>Te<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</inf> (CST)/CdTe absorbers PV devices in an attempt to identify processes that improve CdTe PV throughput and performance. Developing a better understanding of how these Different layering can affect CdTe absorber growth and fabrication will forge a path for further innovation. Preliminary investigation of three alloying profiles revealed interesting correlations between CdSe thickness and open circuit voltage as well as to short circuit current. The introduction of CdSe saw positive correlation to open circuit voltage and an inverse correlation to short circuit current. Indicating possible residual CdSe left at the front after CdCl<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> processing may help device voltages, but too much would parasitically absorb and hurt current collection.