Graded Cadmium Selenide Telluride Absorber Thickness, Back Surface Passivation, and Organic Hole Transport Layers: Interactions in Open-Circuit Voltage and Fill Factor

A photovoltaic device optimization experiment which was designed to probe interactions between graded cadmium selenide telluride (CdSeTe) absorber thickness (1.0 µm to 3.3 µm), CdSeTe back surface chemical state (acid-etched, base-etched, or unetched crossed with 250°C thermal processing toggle), organic hole transport layer (none, Li-doped poly-TPD, Li-doped PTAA, or undoped PVK), and device light soak state (with or without 24 hour, 1 Sun light soak) was performed and the results are discussed herein. Broad trends in the full data set are analyzed using a full factorial least-squares-fit linear regression model. In the current density versus voltage characteristic outputs of open-circuit voltage and fill factor, CdSeTe back surface preparation and organic hole transport material process inputs interact strongly with CdSeTe absorber thickness; process parameters associated with absorber back surface passivation have much stronger effects on device performance in the case of thin CdSeTe absorbers, with a 340-mV open-circuit voltage difference between samples that were passivated using the no-surface-etch/no-thermal-process condition versus the samples passivated with the chemically basic surface etch sequence and pre-back-contact thermal process when device absorbers are 1.0 µm.