Thermal and Mechanical Stability of Laminated Perovskite Solar Cells

Perovskite solar cell (PSC) operational lifetimes have increased, but stability remains a major challenge for commercialization. Key stability issues for PSCs include chemical instability under light and heat, and mechanical failure modes such as delamination or fracture. Laminated PSCs (L-PSCs), created by independently processing the hole and electron transport sides of the solar cell and laminating them together, offer unique passivation, transport, and contact layer combinations. This processing method minimizes thermal and chemical stresses on the perovskite layer during processing of other layers in the cell and provides inherent self-encapsulation between two glass substrates, which can be leveraged to improve stability. However, to date, the thermal and mechanical properties of L-PSCs have not been widely studied. In this study, we measured the thermal cycling stability and interfacial mechanical properties of L-PSCs for the first time. L-PSCs withstood thermal cycling testing (TC50) without failure, with all the devices increasing in power conversion efficiency post-TC50. The champion device increased from an initial electrical performance of 18.4% to 20.0% after TC50. To quantify the mechanical properties of the device stack, we measured the interfacial toughness of aged (non-thermally cycled) and TC50 tested device stacks. Minimal changes in the interfacial toughness of the device stacks were observed with TC50 testing (0.27 ± 0.05 J/m<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> non-TC50 and 0.20 ± 0.04 J/m<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> post-TC50). This study demonstrates the impressive thermal and mechanical stability of L-PSCs with no additional encapsulation. Even after thermal cycling, the L-PSCs are on par in electrical performance and mechanical toughness with pristine non-laminated PSCs and can be a route to avoid critically weak interfaces that hamper commercialization, like C60 in high performing devices.