Design and implementation of AXI interconnect based SerDes architecture in NoC

Abstract High-speed data communication is essential in tackling the ever-increasing pressure on complex System-on-Chip (SoC) designs to process data more quickly within Network-on-Chip (NoC) architectures. In this research work, we propose the SerDes-based AXI Interconnect architecture to be implemented in overcoming major bottlenecks of the present NoC communication system, which face scalability and high-speed data transmission problems. This work fills the gap by taking a holistic approach to resolve deficiencies in legacy protocols by providing an improved, scalable, and low-power solution that makes it suitable for today’s real-time processing applications. The approach includes advanced Serializer/Deserializer (SerDes) technology with AXI Interconnect, which is a parallel-to-serial data converter that will help increase the overall data transfer rates. This architecture is unique as it integrates the AXI protocol with an 8-to-1 serializer and 1-to-8 deserializer connected with flexible routing. It is optimized for maximum data throughput at the lowest power. Further, data interoperates over NoC for scalability and performance and features an XY routing algorithm with virtual channel buffers and a crossbar switch. Simulation and validation were carried out on the Zynq UltraScale+ SoC platform, which shows that the proposed NoC architecture has advantages in data throughput enhancement, low latency, and reduced power consumption over existing state-of-the-art systems (HiFMP, Ring-based hybrid NoC, and FFTM-2D NoC). The resulting architecture, with 1% resource utilization and a power consumption of 0.592 watts, performs better than other state-of-the-art designs with respect to both metrics.