A graph-theoretic chiplet planning methodology for complex signal processing systems

The stringent demands for high performance, low power consumption, and cost-effectiveness in complex signal processing systems, particularly in radar and modern communication applications, have rendered chiplet-enabled design an inevitable trend. However, chiplet planning represents an NP-hard combinatorial optimization problem involving multiple dimensions including functional partitioning, chiplet selection, function mapping, and Die-to-Die (D2D) interconnect design, creating an urgent demand for efficient automated design methodologies. A graph theory-based approach to address these challenges is proposed in the manuscript. The methodology begins by abstracting the target complex signal processing application into an application graph that captures computational and communication requirements. A comprehensive chiplet library is established, encompassing heterogeneous chiplets with detailed PPA specifications, alongside a diverse D2D interface library. Using simulated annealing as the chiplet optimization engine, the method iteratively optimizes both the mapping of functional units to chiplet instances and the selection of D2D interfaces. The proposed method's effectiveness in generating feasible chiplet partitioning solutions under different system scales is demonstrated using a parameterized digital array radar front-end processing system as a benchmark case, with all constraints being satisfied. The results indicate satisfactory adaptability to complexity variations in different application scenarios. The presented graph-based planning methodology offers a systematic and automated solution for chiplet design in complex signal processing systems, demonstrating both theoretical significance and practical implementation potential.