RESEARCH TO METHODS IMPLEMENT THE VITERBI DECODER FOR BCH CODES ON FPGA

The paper considers approaches to the implementation of the Viterbi decoder for BCH codes. Various ways of reconstructing the most plausible codeword are being considered. The scheme of the Viterbi decoder for implementation on FPGAs is given.

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Publication Details

Published
2025-06-15
DOI
https://doi.org/10.21667/978-5-7722-0425-2-26-30
Primary Topic
Error Correcting Code Techniques
Type
article
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article

RESEARCH TO METHODS IMPLEMENT THE VITERBI DECODER FOR BCH CODES ON FPGA

Aleksei Ovinnikov, Nikita Vinogradov
Error Correcting Code Techniques
article

RESEARCH TO METHODS IMPLEMENT THE VITERBI DECODER FOR BCH CODES ON FPGA

Aleksei Ovinnikov, Nikita Vinogradov
article en

Abstract

The paper considers approaches to the implementation of the Viterbi decoder for BCH codes. Various ways of reconstructing the most plausible codeword are being considered. The scheme of the Viterbi decoder for implementation on FPGAs is given.

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Error Correcting Code Techniques
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RESEARCH TO METHODS IMPLEMENT THE VITERBI DECODER FOR BCH CODES ON FPGA — Aleksei Ovinnikov, Nikita Vinogradov · (2025) | TGRS Research Map | TGRS