A Taxonomy of the High-Level Synthesis Ecosystem for Heterogeneous FPGA Systems

Domain-specific accelerators on Field-Programmable Gate Arrays (FPGAs) have been identified as one potential solution to continue the performance scaling after Moore’s Law ends. However, the design of such accelerators is cumbersome, leading to limited productivity and reduced adoption rates, especially in heterogeneous FPGA systems. Thus, this survey investigated hardware design approaches suited for heterogeneous system developers. High-Level Synthesis (HLS) has been identified as the most fitting category for this objective. Currently, we see the creation of many new HLS-related tools that are hard to classify according to conventional taxonomies. Therefore, this work establishes an explicit definition for HLS approaches based on intended usage. The definition combines the classification of hardware design abstractions with parallel programming models to identify suitable approaches unambiguously. The resulting HLS-related tools are categorized and presented according to a newly developed taxonomy. This taxonomy unifies the current vast ecosystem of HLS-related frameworks, including conventional HLS tools as Backends, embedded Domain Space Exploration (DSE) approaches and system-level integrating tools.