Buffer Size Impact on End-to-End DNN Acceleration in Near-Bank DRAM-PIM Systems

Processing-in-Memory (PIM) helps reduce DRAM access bottlenecks in accelerating Deep Neural Networks (DNNs). Industrial solutions like SK Hynix GDDR6-AiM [1] place processing cores (PIMcores) near DRAM banks to lower data movement and latency. However, current near-bank PIM designs face two key limitations: (1) PIMcores mainly support multiply-accumulate (MAC) operations, while other tasks are handled by the host CPU or GPU, causing heavy host-PIM traffic. (2) The buffer capacity is limited (e.g., 2KB global buffer per channel [1]), reducing opportunities for data reuse.