Hybrid SORN Cross-Correlation Architecture for Low-Complexity FPGAs

In this work, a novel signal processing approach for the efficient computation of the cross-correlation operator on low-complexity FPGAs is presented. Sets-Of-Real-Numbers (SORNs) arithmetic is exploited to build resource-efficient multipliers that are carefully injected into the hardware architecture. By this measure, a significant decrease of arithmetic hardware requirements is achieved. Especially, in the scope of low-complexity FPGAs, this depicts an enormous advantage, as these devices usually only have a few or even no specific arithmetic hardware accelerators, such as DSP blocks, at all. In order to smoothly integrate these special multipliers, additional conversion functions are needed to handle the number format transformation between SORNs and the fixed-point (FxD) data representation. For the evaluation, several cross-correlation-related hardware architectures with different number formats, data types, and multipliers are taken into account. Out of this, the proposed SORN-based implementation turns out to achieve extremely high performance regarding the resulting signal quality. In terms of the resource utilization, it clearly outperforms the traditional FxD-based architectures. Hence, SORN-based multipliers identify as a powerful extension for calculating the cross-correlation on low-complexity FPGAs.