Improving CPU Energy Efficiency for Low Latency Use Cases With Software-Defined Core Labeling

In this paper, we address the energy efficiency problems in general-purpose servers used for low-latency usecases. In usecases with strict latency requirements, power-saving features of Central Processing Unit (CPU) such as CPU idle are typically disabled to achieve the strict latency requirements, sacrificing energy efficiency. We determine that this problem arises since the task scheduler of Operating System (OS) and CPU idle control functions focus on generality and fairness. As a result, even latency-critical tasks cannot avoid high wake-up latency caused by deep CPU idle states or being delayed by best-effort tasks. To mitigate this, we propose several policy changes. First, the task scheduler should separate cores into those handling latency-critical tasks and those handling best-effort tasks. Second, instead of predicting appropriate CPU idle states on the basis of assigned tasks, the system should assign tasks to cores with predetermined CPU idle states. To implement this policy, we introduce a method called software-defined labeling, where cores are categorized as performance-oriented or energy-efficient. Performance-oriented cores execute latency-critical tasks with CPU idle disabled, while energy-efficient cores execute best-effort tasks with CPU idle enabled. This approach ensures energy efficiency without compromising latency requirements since latency-critical tasks are not affected by high wake-up latency and best-effort tasks do not limit the power-saving effect of CPU idle. Evaluations using virtualized Radio Access Network (vRAN) as a low-latency usecase demonstrate that our method avoids latency violations that occur with default CPU idle enabled methods and has lower power consumption than CPU idle disabled methods, which are typically used in low-latency usecases.

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Publication Details

Journal
IEEE Access
Published
2025-01-01
DOI
https://doi.org/10.1109/access.2025.3603713
Citations
1
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
2.27
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article

Improving CPU Energy Efficiency for Low Latency Use Cases With Software-Defined Core Labeling

Ko Natori, Kei Fujimoto, Ikuo Otani
1 citations
IEEE Access
Parallel Computing and Optimization Techniques
2.27
article

Improving CPU Energy Efficiency for Low Latency Use Cases With Software-Defined Core Labeling

Ko Natori, Kei Fujimoto, Ikuo Otani
article en
1 citations

Abstract

In this paper, we address the energy efficiency problems in general-purpose servers used for low-latency usecases. In usecases with strict latency requirements, power-saving features of Central Processing Unit (CPU) such as CPU idle are typically disabled to achieve the strict latency requirements, sacrificing energy efficiency. We determine that this problem arises since the task scheduler of Operating System (OS) and CPU idle control functions focus on generality and fairness. As a result, even latency-critical tasks cannot avoid high wake-up latency caused by deep CPU idle states or being delayed by best-effort tasks. To mitigate this, we propose several policy changes. First, the task scheduler should separate cores into those handling latency-critical tasks and those handling best-effort tasks. Second, instead of predicting appropriate CPU idle states on the basis of assigned tasks, the system should assign tasks to cores with predetermined CPU idle states. To implement this policy, we introduce a method called software-defined labeling, where cores are categorized as performance-oriented or energy-efficient. Performance-oriented cores execute latency-critical tasks with CPU idle disabled, while energy-efficient cores execute best-effort tasks with CPU idle enabled. This approach ensures energy efficiency without compromising latency requirements since latency-critical tasks are not affected by high wake-up latency and best-effort tasks do not limit the power-saving effect of CPU idle. Evaluations using virtualized Radio Access Network (vRAN) as a low-latency usecase demonstrate that our method avoids latency violations that occur with default CPU idle enabled methods and has lower power consumption than CPU idle disabled methods, which are typically used in low-latency usecases.

IEEE AccessVol. 13
NTT (Japan) (JP)
Affordable and clean energy
Openalex Percentile: Top 12%
Parallel Computing and Optimization Techniques
2.27
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Improving CPU Energy Efficiency for Low Latency Use Cases With Software-Defined Core Labeling — Ko Natori, Kei Fujimoto, et al. · IEEE Access (2025) | TGRS Research Map | TGRS