Chip size dependent dynamic behavior of SiC MOSFETs with edge termination

• The dynamic behavior of SiC MOSFETs was analyzed based on the active-to-termination area ratio • During turn-off switching, slower dV/dt was observed in smaller chips due to limited C DS charging current • The dV/dt reversal phenomenon appeared as the edge termination area increased relatively • The C DS charging delay in edge termination limited the possible switching frequency of smaller devices • Despite higher sinking-sourcing currents, HSS gate drivers showed limited effectiveness in smaller MOSFETs This study investigates the impact of the active-to-termination area ratio on the dynamic behavior of SiC MOSFETs. As the chip size decreases, the turn-on speed increases due to the reduced input capacitance. However, during the turn-off transient, a dV/dt reversal effect is observed, in which the switching speed decreases despite the overall reduction in parasitic capacitance. This effect arises because, in smaller devices, the edge termination region becomes relatively larger compared to the active region, causing a greater portion of the drain current to flow into the termination region. As a result, the charging of the drain-to-source capacitance in the active region, which dominates the switching transition, slows down. Experimental and mixed-mode simulations confirm that this effect is more pronounced at lower current densities. The study further examines the effect of gate driver capability, showing that a gate driver with high sinking/sourcing capability only maximizes switching frequency. Additionally, thermal resistance and drain-to-source capacitance charging delay limit the maximum switching frequency in smaller devices. These results demonstrate that the active-to-termination area ratio significantly influences the switching characteristics of SiC MOSFETs, particularly in turn-off behavior and frequency limitations.